1. Field of the Invention
The present invention relates to a data bus line control circuit. More particularly, it relates to a data bus line control circuit which enables both 8K refresh operation and 4K refresh operation to be performed in one element.
2. Description of the Prior Art
As a word line form has been increasingly developed from a metal strapping method to a sub word line scheme, a memory cell array and a global data bus line have been used as a structure of FIG. 1.
FIG. 1 schematically illustrates a connection method between a local data bus line and a global data bus line, and representatively illustrates a structure of 64M dynamic random access memory (DRAM).
Referring to FIG. 1, a memory element (i.e., DRAM) includes: a memory unit; a plurality of row decoders 10, 12, 14, 16 and 18 for selecting the memory unit; a plurality of X-holes 20, 22, 24, 26, 28, 30 and 32 for controlling a row path; a data bus line (i.e., local data bus (LDB) line and a global data bus (GDB) line) which is used as a path means for reading a data of the memory unit or writing a data in the memory unit; and a global data bus (GDB) sense-amp for amplifying the data loaded on the global data bus line.
Each memory unit is comprised of 256 row word lines and 104 column bit line pairs. A memory unit of a row (X) decoder side is comprised of a word line of 256-row and a bit line pair of 88-column.
Here, the local data bus line is connected to a bit line, and the global data bus line is connected to a global data bus sense-amp.
Also, a symbol bs_X indicates a signal for connecting a local data bus line to a global data bus line by n-channel metal-oxide semiconductor (NMOS) transistor (not shown), symbols BisL (i.e., block isolation selection low) and BisH (i.e., block isolation selection high) indicate signals for connecting a bit line to a bit line sense-amp by NMOS transistor (not shown).
FIG. 2 is a detailed circuit diagram of xe2x80x9cAxe2x80x9d part of FIG. 1, and illustrates a structure according to a folded bit line method. FIG. 3 is a timing diagram of signals related to FIGS. 1 and 2.
Referring to FIGS. 2-3, if one word line W/L(n) among word lines of a sub block (e.g., this is set to a sub block 15) selected by a row address combination is enabled, data of a cell involved to the enabled word line are loaded on each bit line and each bit line bar, receive an amplification operation of a bit line sense-amp by an active operation of block isolation selection signals BisH(16) and BisL(15), and are loaded on a plurality of local data bus lines by a column line Yi (n) selected by a column (Y) address.
The data loaded on the local data bus line are loaded on a global data bus (GDB) line through a plurality of switches T1, T2, T3 and T4 being opened by an active operation of signals bs_X(15) and bs_X(16) which are both signals toward the selected sub block 15.
According to the above data bus line control method, only one operation between 8K refresh operation and 4K refresh operation can be achieved.
In other words, since global data bus (GDB) lines are connected to local data bus (LDB) lines of all 256K sub blocks, 8K refresh operation is possible, but 4K refresh operation is impossible. That is, operation simultaneously selecting other block cannot be achieved.
For example, if the two blocks 256k_block(0) and 256k_block(16) are simultaneously selected, a global data bus line connected to a local data bue line involved to a block 256k_block by signals bs_X0 and bs_X1 is connected to a local data bus line of 256k_block side by signals bs_X16 and bs_X17. As a result, a data collision occurs in a 4K refresh mode structure wherein two blocks are simultaneously selected.
Accordingly, the present invention is directed to a data bus line control circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
It is an objective of the present invention to provide a data bus line control circuit which prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected.
To achieve the above objectives, a data bus line control circuit according to the present invention includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks, amplified by a bit line sense-amp, to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objective and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.